The present invention relates to a semiconductor memory device, and particularly to a bitline sense amplifier circuit for a semiconductor memory device using an under_drive technique. More particularly, the present invention relates to a bitline sense amplifier circuit for a semiconductor memory device that can perform an under_drive operation stably even in the case of a change in the level of an external power supply voltage.
The continuous scaling-down of a line width and a cell size is accelerating the reduction of the level of a power supply voltage in a semiconductor memory chip, which necessitates design technology for satisfying the performance required in a low-voltage environment.
At the present time, most semiconductor memory chips supply a voltage for an operation of an internal circuit by using an internal voltage generator circuit that generates an internal voltage by the use of an external voltage (i.e., a power supply voltage). Particularly, memory devices using a bitline sense amplifier, such as DRAMs, use a core voltage VCORE and a ground voltage VSS to detect cell data.
When an wordline is selected and enabled by a row address, data of memory cells connected to the selected wordline are transferred to bitlines and a bitline sense amplifier senses and amplifies a voltage difference between a pair of bitlines.
In general, because thousands of bitline sense amplifiers operate at the same time, a large amount of current is supplied to a ground voltage terminal VSS, which is used to drive pull-down power lines (generally called ‘SB’) of the bitline sense amplifiers, at a time. This causes a sudden increase in the voltage level of the ground voltage terminal VSS.
However, a logic decision level for determining whether cell data are logic ‘high’ or logic ‘low’ decreases as the level of a power supply voltage for operating bitline sense amplifiers decreases.
Thus, the level of a ground voltage VSS, which increases suddenly during the operation of bitline sense amplifiers, becomes higher than the logic decision level. In this case, a logic ‘low’ level of cell data may be misinterpreted as a logic ‘high’ level that indicates the need of amplification of the cell data level.
An under_drive technique has been adopted to overcome the above limitation. The under_drive technique drives a pull-down power line of a bitline sense amplifier (i.e., an SB power line) by an under_drive voltage VBB2, which is lower than a ground voltage VSS and is generally between a back-bias voltage VBB and the ground voltage VSS, for a predetermined time at an initial operation stage of the bitline sense amplifier (i.e., at a stage after charge-sharing between a cell and a bit line).
FIG. 1 is a circuit diagram of a conventional bitline sense amplifier circuit using an under_drive technique.
Referring to FIG. 1, the conventional bitline sense amplifier circuit using an under_drive technique includes a bitline sense amplifier 110, an upper bitline equalizer 120, a lower bitline equalizer 170, an upper bitline separator 130, a lower bitline separator 150, a bitline precharger 140, a column selector 160, and a bitline sense amplifier power line driver 100, regardless of the use of the under_drive technique.
The upper bitline separator 130 separates/connects an upper memory cell array and the bitline sense amplifier 110 in response to an upper bitline separation signal BISH. Likewise, the lower bitline separator 150 separates/connects a lower memory cell array and the bitline sense amplifier 110 in response to a lower bitline separation signal BISL.
When an enable signal is activated to drive a pull-down power line SB and a pull-up power line RTO at a predetermined voltage level, the bitline sense amplifier 110 senses a voltage difference between a pair of bitlines BL and BLB, which are in a charge-sharing state and have a minute voltage difference therebetween, and amplifies a voltage of one of the bitlines BL and BLB and a voltage of the other of the bitlines BL and BLB respectively to a ground voltage VSS and a core voltage VCORE.
The upper bitline equalizer 120, the lower bitline equalizer 170, and the bitline precharger 140 precharge the bitlines BL and BLB with a bitline precharge voltage VBLP, which is generally VCORE/2, in response to a bitline equalization signal BLEQ, after the completion of the sensing/amplifying and re-storing operations on the bitlines.
When a read command is applied, the column selector 160 transfers data, which are sensed/amplified by the bitline sense amplifier 110, to segment data buses SIO and SIOB in response to a column selection signal YI. On the other hand, when a write command is applied, the column selector 160 transfers external input data to an upper memory cell or a lower memory cell in response to a column selection signal YI.
The bitline sense amplifier power line driver 100 includes a normal pull-up power line driver 102, an overdrive pull-up power line driver 103, a normal pull-down power line driver 106, and an under_drive pull-down power line driver 107. The normal pull-up power line driver 102 drives the pull-up power line RTO by the core voltage VCORE in response to a normal pull-up power line drive control signal SAP1. The overdrive pull-up power line driver 103 drives the pull-up power line RTO by an external power supply voltage VDD or a pumping voltage VPP in response to an overdrive pull-up power line drive control signal SAP2. The normal pull-down power line driver 106 drives the pull-down power line SB by the ground voltage VSS in response to a normal pull-down power line drive control signal SAN1. The under_drive pull-down power line driver 107 drives the pull-down power line SB by an under_drive voltage VBB2 in response to an under_drive pull-down power line drive control signal SAN2.
Herein, the normal pull-up power line drive control signal SAP1 and the overdrive pull-up power line drive control signal SAP2 are defined as ‘low’ active pulses and thus PMOS transistors P1 and P2 are used to drive the pull-up power line RTO. This, however, is merely exemplary and NMOS transistors may also be used to drive the pull-up power line RTO.
Likewise, the normal pull-down power line drive control signal SAN1 and the under_drive pull-down power line drive control signal SAN2 are defined as ‘high’ active pulses and thus NMOS transistors N1 and N2 are used to drive the pull-down power line SB. This, however, is merely exemplary and PMOS transistors may also be used to drive the pull-down power line SB.
FIG. 2 is a signal timing diagram illustrating an operation of the conventional bitline sense amplifier circuit illustrated in FIG. 1.
Referring to FIG. 2, the operation of the conventional bitline sense amplifier can be divided as follows:
Because data stored in a cell array are not yet transferred to the bitlines BL and BLB, the bitlines BL and BLB maintain a precharge voltage HALF_VCORE (e.g., 0.55 V) at an initial operation stage ({circle around (1)}).
Thereafter, when the data stored in the cell array are transferred to the bitlines BL and BLB, the bitlines BL and BLB have a minute voltage level difference therebetween for a predetermined time ({circle around (2)}).
Thereafter, when the voltage level difference between the bitlines BL and BLB is a predetermined value or more due to the data transferred from the cell array, the bitline sense amplifier 110 performs a sense/amplification operation such that the bitlines BL and BLB have a large voltage level difference therebetween ({circle around (3)}).
The pull-up power line RTO and the pull-down power line SB must be driven already when the bitline sense amplifier 110 starts to operate. The bitline sense amplifier circuit illustrated in FIG. 1 uses both of an overdrive technique and an under_drive technique. Therefore, during the sense/amplification operation, the voltage of the bitline BL is suddenly amplified up to a level corresponding to the under_drive voltage VBB2 ({circle around (4)}) and the voltage of the bitline BLB suddenly increases up to a level corresponding to the external power supply voltage VDD ({circle around (5)}).
In this way, by using not only the overdrive technique but also the under_drive technique, the conventional bitline sense amplifier circuit for a semiconductor memory device can stably perform a bitline sense/amplification operation even when the level of the external power supply voltage VDD decreases.
However, because the under_drive voltage VBB2 must be lower than the ground voltage VSS and higher than the back-bias voltage VBB, the conventional bitline sense amplifier circuit must additionally generate the under_drive voltage VBB2 in order to use the under_drive technique in a general semiconductor memory device.
FIG. 3 is a block diagram of an under_drive voltage generating unit for generating an under_drive voltage in a conventional bitline sense amplifier circuit using an under_drive technique.
Referring to FIG. 3, the under_drive voltage generating unit for generating an under_drive voltage VBB2 includes an under_drive voltage detector 300 and an under_drive voltage generator 320. The under_drive voltage detector 300 detects the level of an under_drive voltage VBB2. The under_drive voltage generator 320 generates the under_drive voltage VBB2 in response to an output signal VBB2_DET of the under_drive voltage detector 300.
The under_drive voltage generator 320 includes an oscillator 322 and a pumping unit 324. The oscillator 322 generates an oscillation signal OSC in response to the output signal VBB2_DET of the under_drive voltage detector 300. The pumping unit 324 generates the under_drive voltage VBB2 by performing a charge pumping operation in response to the oscillation signal OSC of the oscillator 322.
However, as described above, the under_drive voltage generating unit is configured to generate the under_drive voltage VBB2 that maintains a predetermined voltage level regardless of a change in the level of the external power supply voltage VDD or the operation of a semiconductor memory device.
Thus, in order to stably perform an under_drive operation, the under_drive voltage generating unit must generate the under_drive voltage VBB2 by the corresponding driving force when the under_drive voltage VBB2 is most used in the semiconductor memory device, that is, when all the banks included in the semiconductor memory device perform a sense/amplification operation at the same time.
However, if a constant driving force (i.e., the strongest driving force) is always used to generate the under_drive voltage VBB2 even when there is a change in the number of banks performing an operation of the semiconductor memory device, particularly a sense/amplification operation, the under_drive voltage VBB2 is generated by the driving force more than necessary, which causes a waste of current.
For example, if the number of banks performing a sense/amplification operation is half of the number of all the banks included in the semiconductor memory device, it is unnecessary to generate the under_drive voltage VBB2 by the driving force corresponding to the case where all the banks included in the semiconductor memory device perform a sense/amplification operation at the same time.
Also, the level of the external power supply voltage VDD may become lower than a predetermined voltage level due to a change in the PVT (process, voltage and temperature) of the semiconductor memory device. In this case, the under_drive voltage VBB2 may have a voltage level lower than the predetermined voltage level because a predetermined driving force fails to be maintained.
If the under_drive voltage VBB2 may have a voltage level lower than the predetermined voltage level, that is, if the under_drive voltage VBB2 has a voltage level similar to the level of the ground voltage VSS, the conventional bitline sense amplifier may misinterpret a logic ‘low’ level of cell data as a logic ‘high’ level that indicates the need of amplification of the cell data level. That is, there is no effect of the use of an under_drive technique.